1. Field of the Invention
The present invention generally relates to overcoming problems encountered when interconnecting plural computers on a single bus. Specifically, a method and apparatus are provided which allow plural computers, each including a central arbiter for determining access and priority to their internal system bus, to be interconnected and share a common bus.
2. Background of Related Art
Interconnected computer systems are becoming increasingly popular due to the increase in available processing power and other economies of scale. It is often desirable to interconnect several substantially complete computer systems together on the same bus. For example, a personal computer such as a PS/2, manufactured by the IBM Corp., may be designated as the host computer with other PS/2 computers or workstations, such as the RISC System/6000 (PS/2 and RISC System/6000 are trademarks of IBM) as the interconnected subsystem. Of course, the RISC System/6000 machine could also be designated as the host system with other RISC System/6000 computers or PS/2 computers configured as the subsystems. Regardless of the desired configuration, each computer (whether a stand alone unit, or a computer system on a board) will have a central arbiter that determines which of the busmaster devices, e.g. central processing unit (CPU), direct memory access (DMA), small computer system interface (SCSI), or the like, can access the slave devices, such as the memory, floppy disk, serial port, I/O peripherals, or the like, through the system bus.
Referring to FIG. 1, a typical configuration is shown wherein a central arbiter 1 is used to arbitrate access to a Micro Channel bus 11 (Micro Channel is a trademark of IBM Corp.). Busmaster devices 3,5,7 each include a request arbiter with an assigned priority value. SCSI busmaster 7 controls a hard disk 9 and DMA 5 is a direct memory access controller. Slave devices 13, 15, 17, 19 will transfer information between a corresponding busmaster device when the request arbiter in the busmaster device successfully arbitrates for access to the bus. For example, it may be desired for information to be transferred from hard disk 9 to the memory 13. The SCSI busmaster 7 will have to arbitrate for access to bus 11 in order to complete the transfer of data.
Several types of arbitration schemes exist and have been used to access the bus for a busmaster device. IBM TDB "High-Speed Processor Bus Arbitration" shows a typical arbitration scheme which uses a signal to control the timing of when a new busmaster (the one that has received a Bus.sub.-- Grant) can take control of the bus. IBM TDB "Interchip Arbitration Design" describes an interchip arbitration arrangement which uses rotating priority values and includes a "look ahead" feature to permit fast arbitration. IBM TDB "Improvement on Parallel Arbitration Scheme" discusses an arbitration scheme wherein ownership of the bus is determined by a distributed priority scheme, but the current bus owner remains owner until a request from another device is present. The current owner then defines a competition period for the bus which determines the new owner of the bus. U.S. Pat. No. 4,734,909 describes a bus arbitration system wherein the arbitration is time phased, or partitioned in time to transpire across a number of contiguous cycles. If each of the time phased arbitration cycles transpire on the same bus communication line, then a large number of contending devices can be arbitrated amongst a small number of communication lines (IC device I/Os).
FIG. 2 is a timing diagram for a typical arbitration scheme. At point A, which is the default state, the CPU (arbitration level F) owns the bus. Generally, the CPU will have the lowest arbitration priority since it owns the bus during the default state. At point B, a peripheral device (busmaster) needs the bus and drives a PREEMPT# signal active which indicates that a request for the bus has occurred. The central arbiter recognizes the active PREEMPT# signal and begins an arbitration cycle at point C. The requestor(s) then arbitrate for access to the bus by comparing their priority values. At point D, the requestors have completed the arbitration and determined that peripheral device 5, e.g. DMA 5 of FIG. 1, has won access to the bus. The central arbiter then ends the arbitration cycle at point E and the bus is granted to DMA 5. Upon winning the bus, DMA 5 releases (deactivates) its PREEMPT# signal and drives a BURST# signal active to maintain ownership of the bus. At point F, the peripheral device (DMA 5) is finished with the bus and releases the BURST# signal. The central arbiter recognizes the release of the bus and runs an arbitration cycle at point G and if there are no other requests, bus ownership returns to the CPU by default (point H).
However, it can be seen that problems will arise when it is desired to connect plural computer systems through a single bus, since each computer will have a central arbiter. Of course, the central arbiter could be removed from the attached computer subsystems, but this would mean costly reworking of the subsystem, since the central arbiter is usually packaged along with other necessary components on a single integrated circuit device package, i.e. a single chip. Thus, in order to preserve the subsystem function, the chip containing the central arbiter would have to be reworked to remove that function. It can be seen that an addition to the subsystem that would cause the central arbiter to act like a slave arbiter and thus allow interconnection of plural computer subsystems to a single bus along with a host computer would be very desirable. IBM TDB "Shared Master/Slave Device" discusses a device which includes master and slave operations. This device allows for the occurrence of slave operations at any time, but does not inhibit the device's effectiveness as a busmaster. IBM TDB "Dual Master Bus Isolator" discusses hardware logic circuitry that transparently interconnects two microprocessor buses by treating each bus as a virtual address when one bus accesses the other. IBM TDB "Movable Bus Arbiter and Shared Bus Address" describes a method that allows sharing of bus arbitration between two bus devices. Two processors can share the same bus address and arbitration function so that their existence is transparent to other I/O devices on the bus. It can be seen that these references provide transparency to bus devices when two processors are used. However, a problem still exists in the prior art wherein multiple computer subsystems cannot be interconnected without reworking the chip set.